1. Field of the Invention
This invention relates generally to the fabrication method for manufacturing the semiconductor devices supported on a silicon substrate. More particularly, this invention relates to novel and improved processing steps to break the silicon wafer into a plurality of semi-conductor chips to eliminate the wastes of wafer surface areas and edge damages such as chipping or cracks resulting from current dicing technique. The breaking process can also be more precisely conducted.
2. Description of the Prior Art
The use of dicing saw techniques for cleaving the semiconductor chips or dies from a silicon wafer resulting in wastes of precious and limited wafer surface areas. Additionally, the techniques often lead to die edge chipping or cracks which eventually cause a reduction in production yield, a cost increase in manufacture and degradation in product reliability. The dicing saw techniques involve the use of rotating diamond wheel to scribe the wafers and then break the wafer into a plurality of small pieces, i.e., the chips. The techniques may also involve the use of a to semi-scribe the wafers and then break the wafers into chips by rolling a rubber wheel on the wafers. These approaches may includes laser scribing or mechanical scribing and cleave. In addition to these methods, there are several prior art patents with various attempts to solve the problems associated with dicing techniques and to provide improved IC chip productivity by applying a better wafer breaking process.
In U.S. Pat. No. 5,458,269, entitled "Frangible Semiconductor Wafer Dicing Method Which Employs Scribing and Breaking" (issued on Oct. 17, 1995), Loomis disclosed a method to separate a semiconductor wafer. The method is carried out by applying a controlled, adjustable stain and strain rate by use of a break wheel to break a frangible semiconductor wafer around previously placed scribe lines formed along surface of the wafer. Special break wheels are applied for applying a resilient breaking force to the wafer in a region straddling the scribe line. The break wheels are used with a tilted surface having a break edge with which the scribe line is aligned prior to the application of the breaking force. The tilted surface is adjustable to provide a variable maximum strain limit. Difficulties of waste of wafer areas are not solved by this invention as it is required extra wafer areas must be used for placing the breaking wheels for the dicing operation.
In U.S. Pat. No. 5,310,104, entitled "Method and Apparatus for Cleaving A Semiconductor Wafer into Individual Die and Providing for Low Stress Die Removal" (issued on May 10, 1994), Zaidel et al. disclose a method and apparatus for cleaving a semiconductor into die. The method is performed by mounting the wafer on an adherent resilient air impermeable membrane which has a flat surface. Cleaving is performed by using air pressure to inflate the membrane to cause bending and tensile stresses on the wafer brought about by its adhesion to the inflating membrane. The stresses cleave the wafer along the scribe marks to form individual die. The die may be easily removed by the application of a vacuum to the membrane. The method of Zaidel et al. requires complex vacuum system and membrane process apparatuses. Production cost and time may also be increased due to the complicated steps of placing the wafer onto the membrane and other additional steps required to achieve the cleaving of the wafers.
In U.S. Pat. No. 5,521,125, entitled "Precision Dicing of Silicon Chips from A Wafer" (issued on May 28, 1996), Ormond et al. disclose a dicing technique for cleaving semiconductor wafers. The dicing technique is carried out by depositing successive layers of silicon oxide in a first and second regions on a surface of a silicon wafer for defining a street having no oxide layers. The oxide layers forming a vertical walls defining the boundary of the streets. A shock absorbing material is deposited in the street forming a concave meniscus. The shock absorbing materials can retard the trajectories of the silicon particles and prevent the particles to set into motion during the process when the wafer is diced into chips. Ormond et al. provide a technique to improve the cleaving of the semiconductor by dicing process. The difficulties arising from applying dicing technology, e.g., wastes of wafer spaces reserved for dicing operation are still not resolved by this patented disclosure.
In U.S. Pat. No. 5,157,001, entitled "Method of Dicing Semiconductor Wafer Along Protective Film Formed in Scribe Lines" (issued on Oct. 20, 1992), Sakuma discloses a dicing technique by forming a protective film buried in the wafer along the scribe lines. The protective film will then protect the edge along the breaking lines such that cracks or damages of the semiconductor chips along the braking edges can be prevented. Again, using the protective film as that disclosed in this patent does not solve the difficulties encountered by applying a dicing method. Similarly, in U.S. Pat. No. 5,314,844, entitled "Method for Dicing a Semiconductor Wafer" (issued on May 24, 1994), Imamura discloses a method for dicing a wafer of III-V compound material without causing chipping and cracks. The method includes a step of forming the scribe lines orthogonal to a crystal place (011) by scribing using grinding and cutting method. Wastes of semiconductor wafer space by applying a grinding and cutting processes is till present in the patented technique.
U.S. Pat. No. 4,179,174 discloses a semiconductor wafer dicing technique in which recessed grooves are formed into the wafer by an etching technique, along lines corresponding to the boundaries of adjacent chips. The surfaces of these etched grooves are then coated with a resin, and the semiconductor is then severed into individual chips. Due to the special technical difficulties typically encountered in the etching process, such technique is however considered as undesirable. Particularly, the undercutting of the masked areas and rounding the bottom of the separation pattern. Due to these difficulties, the etch process is considered as not useful for cleaving the wafer since proper cleaves cannot be obtained when etching processes are employed. (Please refer to the last paragraph in Background of the Invention" Section in U.S. Pat. No. 4,729,971). Because of this teaching away from using etch process for separating a wafer into individual chip, a person of ordinary skill in the art would not consider etching process can provide a feasible solution to the difficulties generally encountered in dicing the wafer into chips.
Therefore, a need still exists in the art of integrated circuit (IC) manufacture for a novel and improved technique to separate the wafer into individual chips. Preferably, this novel technique can be easily incorporated and conveniently applicable in an IC manufacturing process without complicate processing steps. More importantly, it is desirable that the wafer cleaving technique can achieve savings of wafer space to reduce wastes of precious semiconductor surface areas required to be reserved for typical dicing processes. Additionally, the new techniques would provide a method to overcome the undercutting and bottom-rounding difficulties faced by the industry when etching process is applied such that the quality of the IC chips and production cost can be improved by applying the cleaving technology disclosed in this invention.